FIG. 1A schematically illustrates an embodiment of a static random access memory (SRAM) cell 100. The SRAM cell 100 includes a pair of inverters 102 and 104, with the output of inverter 102 coupled to the input of inverter 104, and the output of inverter 104 coupled to the input of inverter 102. Coupling inverters 102 and 104 in this manner results in a self-sustaining memory cell. In addition to the inverters 102 and 104, SRAM cell 100 includes a pair of pass-gate transistors 106 and 108. Pass-gate transistor 106 is coupled to the input of inverter 102 and the output of inverter 104, while pass-gate transistor 108 is coupled to the output of inverter 102 and to the input of inverter 104.
FIG. 1B schematically illustrates an ideal SRAM cell 150 that is a semiconductor implementation of the SRAM cell 100. The SRAM cell 150 includes a pair of pass-gate transistors 170 and 176, a first inverter made up of pull-down transistor 178 and pull-up transistor 180, and a second inverter made up of pull-down transistor 172 and pull-up transistor 174. In one embodiment, the pass-gate and pull-down transistors are NMOS and the pull-up transistor is PMOS. SRAM cell 150 is thus a six-transistor SRAM cell, because it includes a total of six transistors. Normally, all six transistors in SRAM cell 150 are of the same construction, such as planar transistor or trigate transistors.
The SRAM cell 150 includes several “diffusions” 154, 156, 158 and 160 of variable width W built on a substrate 152. Each diffusion includes at least one source, at least one drain and at least one channel separating each source/drain pair. Also built on substrate 152 are several gate electrodes 162, 164, 166 and 168 of variable gate length H. A transistor is formed at selected places where the gate electrodes overlap with the diffusions. For example, pass-gate transistor 170 is formed at the overlap of diffusion 154 with gate electrode 162, pull-down transistor 172 is formed at the overlap of diffusion 154 and gate electrode 166, and pull-up transistor 174 is formed at the overlap of diffusion 156 and gate electrode 166. SRAM cell 150 is an “ideal” cell because, as explained below, it is difficult, if not impossible, to have diffusions and gate electrodes of constant width in an SRAM cell where all transistors are of the same type.
FIGS. 2A and 2B illustrate a pair of approaches to tuning the relative strengths of the transistors in SRAM cell 150. For SRAM cell 150 to operate in a stable fashion, it is better for the transistors that form SRAM cell 150 to have different strengths: for stable operation, pull-down transistors 172 and 178 may be the strongest, pass-gate transistors 170 and 176 the next strongest, and pull-up transistors 174 and 180 the weakest. For a particular transistor construction, the strength of the transistor is adjusted by changing the width W of the diffusions, the gate length H of the gate electrode, or both. For a given value of W, a larger value of H creates a weaker transistor; similarly, for a given value of H, a larger W creates a stronger transistor. In general, PMOS transistors are weaker than NMOS transistors with the same W and H. The pull-up transistor can have the same W and H as the pass-gate so that the pull-up transistor is the weakest.
FIG. 2A illustrates an embodiment of an SRAM cell 200 in which the width W of the diffusions is changed to vary the strength of the transistor. Thus, diffusion 202 has a first width W1 where it intersects gate electrode 210 to form the pass-gate transistor and a second width W2 where it intersects gate electrode 212 to form the pull-down transistor. Because W1 is smaller than W2, the resulting pass-gate transistor is weaker than the pull-down transistor. Similarly, diffusion 206 is narrower where it intersects gate electrode 216 to form the pass-gate transistor and wider where it intersects gate electrode 214 to form the pull-down transistor. FIG. 2B illustrates an embodiment of an SRAM cell 250 in which the length H of the gate electrodes is varied to vary the transistor strength. Thus, gate electrode 252 has a first width H1 where it intersects diffusion 260 to form the pull-down transistor and a second width H2 where it intersects diffusion 262 to form the pull-down transistor. Because H1 is smaller than H2, the resulting pass-gate transistor is weaker than the pull-down transistor. Similarly, gate electrode 256 is narrower where it intersects diffusion 266 to form the pass-gate transistor and wider where it intersects diffusion 264 to form the pull-down transistor.
The techniques employed in FIGS. 2A and 2B suffer from several problems. Efficient patterning and etching of the diffusions and gate electrodes prefers that both should be straight lines. But varying the width W of the diffusions creates “jogs” 204 and 208, while varying the width H of the gate electrodes also creates jogs 254 and 258. For sub-100 nm technologies, the gate length H and diffusion width W are less than the wavelength of light used to photolithographically pattern the diffusions and gate electrodes, the presence of these jogs substantially increases the complexity of the masks used to pattern the features, as well as the difficulty of properly etching the features once patterned.